Programmable Array Logic

Results: 262



#Item
31Kinematic Analysis of a Space Mechanism—Rendezvous Simulator

Kinematic Analysis of a Space Mechanism—Rendezvous Simulator

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Source URL: www.abhinavjournal.com

Language: English - Date: 2014-01-30 00:14:34
32Chapter 1  Methodology and Example-Driven Interconnect Synthesis for Designing Heterogeneous Coarse-Grain Reconfigurable Architectures Johann Glaser, Clifford Wolf∗

Chapter 1 Methodology and Example-Driven Interconnect Synthesis for Designing Heterogeneous Coarse-Grain Reconfigurable Architectures Johann Glaser, Clifford Wolf∗

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Source URL: www.clifford.at

Language: English - Date: 2013-12-08 09:21:06
33Innovative Logic demonstrate their USB3.0 SuperSpeed IP using Spartan FPGA and TI USB3.0 PHY Innovative Logic Inc.(Inno-Logic, www.inno-logic.com), leading provider of reusable standard based Intellectual Property (IP) a

Innovative Logic demonstrate their USB3.0 SuperSpeed IP using Spartan FPGA and TI USB3.0 PHY Innovative Logic Inc.(Inno-Logic, www.inno-logic.com), leading provider of reusable standard based Intellectual Property (IP) a

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Source URL: www.usb.org

Language: English - Date: 2013-01-04 18:52:10
342013年2月xx日

2013年2月xx日

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Source URL: www.csis.tohoku.ac.jp

Language: English - Date: 2013-02-20 00:31:04
35June 11, 2012  Tohoku University Tohoku University Develops the World’s First 3-D Reconfigurable Spin Logic Chip with Spintronics Technology

June 11, 2012 Tohoku University Tohoku University Develops the World’s First 3-D Reconfigurable Spin Logic Chip with Spintronics Technology

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Source URL: www.csis.tohoku.ac.jp

Language: English - Date: 2012-06-07 22:56:49
36FEATURE OPENCORES: DIY CPUS  Designing and implementing your own CPU or System-on-Chip brings benefits to thousands of researchers and forward-looking businesses, and is being adopted by a growing number of hobbyists. Ri

FEATURE OPENCORES: DIY CPUS Designing and implementing your own CPU or System-on-Chip brings benefits to thousands of researchers and forward-looking businesses, and is being adopted by a growing number of hobbyists. Ri

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Source URL: www.linuxvoice.com

Language: English - Date: 2015-02-09 09:27:26
37FMC Digital I/O (version 2) On the hardware design Tomasz Wlostowski (CERN)  i

FMC Digital I/O (version 2) On the hardware design Tomasz Wlostowski (CERN) i

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Source URL: www.ohwr.org

Language: English
38Computing:91–102 DOIs00607Aligning the representation and reality of computation with asynchronous logic automata Neil Gershenfeld

Computing:91–102 DOIs00607Aligning the representation and reality of computation with asynchronous logic automata Neil Gershenfeld

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Source URL: www.cba.mit.edu

Language: English - Date: 2011-12-17 09:30:36
39Sub-Nanoseconds Time Measurement Systems: USB2.0-TDC Series Device Dual Channel USB2.0-TDC No. of GPX Chips

Sub-Nanoseconds Time Measurement Systems: USB2.0-TDC Series Device Dual Channel USB2.0-TDC No. of GPX Chips

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Source URL: surface-concept.com

Language: English - Date: 2010-05-07 07:43:17
40Cryptography with Asynchronous Logic Automata Peter Schmidt-Nielsen, Kailiang Chen, Jonathan Bachrach, Scott Greenwald, Forrest Green, and Neil Gershenfeld MIT Center for Bits and Atoms, Cambridge, MA

Cryptography with Asynchronous Logic Automata Peter Schmidt-Nielsen, Kailiang Chen, Jonathan Bachrach, Scott Greenwald, Forrest Green, and Neil Gershenfeld MIT Center for Bits and Atoms, Cambridge, MA

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Source URL: www.cba.mit.edu

Language: English - Date: 2011-12-17 09:30:36